The present invention relates to a semiconductor device provided with a power-on reset circuit.
A power-on reset circuit outputs a reset signal that enters an activated state (active) at the time of power-on or at the time of decrease in power supply voltage in order to prevent malfunction of a system. When the reset signal enters an inactivated state (i.e., when reset is released), initialization operation of the system is performed.
As a power-on reset circuit, there is a known comparator that compares a power supply voltage with a reference voltage. For example, Japanese Patent Laid-Open No. 1994-150029 (Patent Document 1) discloses a reset control device that has a comparator for comparing an external power supply voltage supplied to a micro computer with a plurality of reference levels that are mutually different in level.
As other type of power-on reset circuit, there are an enhancement type PMOS (Positive-channel Metal Oxide Semiconductor) transistor, a depletion type NMOS (Negative-channel MOS) transistor, and an inverter that outputs a reset signal (for example, refer to Japanese Patent Laid-Open No. 2012-34101 (Patent Document 2)). The PMOS transistor and the NMOS transistor are connected in series between a power supply node and a ground node. A voltage of a connection node of the PMOS transistor and the NMOS transistor is input to the inverter.